Design of Digital Clock circuit
In digital clock circuit, the 50 Hz, 220 volts ac main sinusoidal signal is shaped into a 50Hz, a 5 volt square wave signal. A divide by 50 counters divides the input 50 Hz signal to a 1 Hz signal. The seconds, divide by 60 counter counts up to 60 seconds (0 to 59). The minutes, divide by 60 counter also counts up to sixty minutes (0 to 59). The hours, decade counter counts from 0 to 9. The flip flop connected to the output of the decade counter is set to 0 or 1 to represent hours from 0 to 9and 10 to 12 respectively.
Figure: Digital clock circuit
Divide by 60 counters
Divide by 60 counters is implemented by cascading two 74HC160A counters. The following diagram shows its implementation.
Figure: Divide by 60 minutes and seconds counter
