8 bit Serial In/ Parallel out shift register
An 8 bit serial in / parallel out register based on an identical D type flip flop is shown;
Figure: 8 bit Serial In/ Parallel out shift register
Implementation on PLD
An 8 bit Serial In/ Parallel out register is implemented using the GAL22V10 PLD. The D flip flop implemented in the OLMC is triggered on the positive clock edge. It also has active high asynchronous set and clear inputs.
Module Right_bit_shift_register
Title ‘8-bit shift register in a GAL22V10’
“Device Declaration
Register Device ‘P22V10’
“Pin Declaration
Clock, Clear Pin 1, 2;
Data, Enable Pin 3, 4;
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 Pin 16, 17, 18, 19, 20, 21, 22, 23 ISTYPE ‘reg.buffer’;
Equations
Q0 := Data & Enable;
[Q1, Q2, Q3, Q4, Q5, Q6, Q7] := [Q0, Q1, Q2, Q3, Q4, Q5, Q6];
[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7].CLK = clock;
[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7].AR = !clear;
Test_Vectors
([Clock, Clear, Data, Enable] -> [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7])
[ .x. , 0 , .x. , .x. ] -> [0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 1 , 0 ] -> [0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 0 , 1 ] -> [0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 1 , 1 ] -> [1 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 0 , 1 ] -> [0 , 1 , 0 , 0 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 1 , 1 ] -> [1 , 0 , 1 , 0 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 0 , 1 ] -> [0 , 1 , 0 , 1 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 1 , 1 ] -> [1 , 0 , 1 , 0 , 1 , 0 , 0 , 0 ];
[ .c. , 1 , 0 , 1 ] -> [0 , 1 , 0 , 1 , 0 , 1 , 0 , 0 ];
[ .c. , 1 , 1 , 1 ] -> [1 , 0 , 1 , 0 , 1 , 0 , 1 , 0 ];
[ .c. , 1 , 0 , 1 ] -> [0 , 1 , 0 , 1 , 0 , 1 , 0 , 1 ];
[ .c. , 1 , 1 , 1 ] -> [1 , 0 , 1 , 0 , 1 , 0 , 1 , 0 ];
[ .c. , 0 , 1 , 1 ] -> [0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ];
END
