Inverting Operation Amplifier
In an inverting amplifier; the output of the voltage changes in opposite direction as that of input voltage. The following figure shows the configuration of Inverting amplifier;
Figure: Inverting operation amplifier
Simulation
The following figure shows the simulation of 741 operation amplifier;
Figure: Simulation of inverting operation amplifier
Serial Communication Based Calculator
Implemented a serial communication based calculator using Proteus. The PIC18F871 PIC was used; it was connected with 20 x 2 alphanumeric LCD. The LCD was used to display the numbers input by the user from a PC connected via serial port with the microcontroller. The below the schematic of the project;
Schematic Design
The below is the schematic design of the project;
Figure: Schematic of Serial communication based calculator
PCB Design
The following shows the PCB design of the project;
Figure: PCB design of serial communication based calculator
Sound Effects:
We have created some sound effects listed below:
1: Echo
2: Delay
3: Multiple delays
4: Multiple echoes
5: Fade in
6: Fade out
1:ECHO:
The Phenomenon produced when a sound reflects from any obstacle delayed by 100 ms.Or in other words, repetition of a sound by reflection of sound waves from a surface. Echo rises in Communication systems, when signals encounter a mismatch in impedance.
Figure:Echo Sound Effect
ALGORITHM:
We are reading a sound clip from a file into a vector, then we produced the delayed version of the sound (delaying it by 100 ms),then we add the two vectors obtaining the resultant echoed sound clip.
Figure: Graphical View of Echo Sound Effect.
2: MULTIPLE DELAYS:
When we add up a sound clip with itself each delayed by different factor,the resultant is multiple delayed sound effect.
Figure: Multiple Echo Sound Effects.
ALGORITHM:
A) Read a sound clip from a file
B) take input from user number of walls , Nwalls.
C) Input distance of each wall into Distance vector
D) Calculate delay of each reflected signal into delays vector.
E) Produce the delayed version of original sound by delaying it by delays[i]
F) Sum up the all delayed vectors. The resultant is multiple delayed signal.
Traffic Light Controller
A road intersection is shown on the diagram; on each section of the road
two sensors determine the presence and arrival of vehicles. Sensor 1 is activated if a car is waiting and Sensor 2 is activated when an arriving vehicle passes over the sensor. The sensors installed on the North and South section of the road are connected together and determine the presence of vehicle(s) on the North-South section of the road. The sensors installed on the East and West section of the road are connected together and determine the presence of vehicle(s) on the East-West section of the Road.
Figure: The traffic signals and sensors at traffic intersection.
Verilog code and test bench files
The following is the Verilog design files and test bench for the traffic light controller;
Code is simulated on ModelSim, synplify and XSV FPGA board;
/*traffic_Controller.v*/
`define S0 3′d0
`define S1 3′d1
`define S2 3′d2
`define S3 3′d3
`define S4 3′d4
`define S5 3′d5
`define S6 3′d6
`define S7 3′d7
`define S8 3′d8
‘define time_base 22′d9
/* 22′d9 is used only for simulation purpose- For 40Mhz operation; the time base
is 0.1 sec.
Change 22′d9 to 22d3999999 for 40Mz frequency */
‘define load_cnt2 9′d449
/* This is timer 1 count value in units if 0.1 sec providing 45 sec delay. */
‘define load_cnt3 6′d49
/*This is the time 2 count value in the units of 0.1 sec, providing 5 sec delay.*/
‘define load_cnt4 9′d249
/*This is the timer 3 count value in the units of 0.1 sec providing 1 sec delay*/
module traffic_controller(clk,
reset_n,
MG1,
MG2,
SR1,
SR2,
MY1,
MY2,
MR1,
MR2,
SG1,
SG2,
SY1,
SY2,
MRT1,
MRT2,
SRT1,
SRT2,
blink
);
/*Declear input and outputs */
input clk;
input reset_n;
input blink;
output MG1;
output MG2;
output SR1;
output SR2;
output MY1;
output MY2;
output MR1;
output MR2;
output SG1;
output SG2;
output SY1;
output SY2;
output MRT1;
output MRT2;
output SRT1;
output SRT2;
/*Declear combinational circuits outputs */
wire adv_cnt2;
wire adv_cnt3;
wire adv_cnt4;
wire res_cnt1;
wire res_cnt2;
wire res_cnt3;
wire res_cnt4;
wire [21:0] cnt1_next;
wire [8:0] cnt2_next;
wire [5:0] cnt3_next;
wire [7:0] cnt4_next;
wire [7:0] cnt5_next;
/* Declear register signals */
reg [21:0] cnt1_reg;
reg [8:0] cnt2_reg;
reg [5:0] cnt3_reg;
reg [7:0] cnt4_reg;
reg [7:0] cnt5_reg;
reg start_timer_1;
reg start_timer_2;
reg start_timer_3;
reg [2:0] state;
reg MG1;
reg MG2;
reg SR1;
reg SR2;
reg MY1;
reg MY2;
reg MR1;
reg MR2;
reg SG1;
reg SG2;
reg SY1;
reg SY2;
reg MRT1;
reg MRT2;
reg SRT1;
reg SRT2;
/*Timer implementation starts here */
assign cnt1_next = cnt1_reg + 1;
always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1′b0)
cnt1_reg <= 22′d0;
else if(cnt_reg == `time_base)
cnt1_reg <= 22′d0;
else
cnt1_reg <= cnt1_next;
end
/* This is a timer 1 programmed for 45 sec in order to facilitate the smooth run of the
main road traffic */
assign adv_cnt2 = (start_timer_1 == 1′b1) & (cnt1_reg == `time_base);
assign res_cnt2 = (cnt1_reg == `time_base) & (count2_reg == `load_cnt2)
assign cnt2_next = cnt2_reg + 1;
always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1′b0)
cnt2_reg <= 9′d0;
else if(res_cnt2 == 1′b1)
cnt2_reg <= 9′d0;
else if(adv_cnt2 == 1′b1)
cnt3_reg <= cnt3_next;
else
cnt2_reg <= cnt2_reg;
end
/*This is the timer 2 programmed for 5 sec. Activating yellow lights for the smoth transitaion while switching from one traffic to another */
assign adv_cnt3 = (start_timer2 == 1′b1) & (cnt1_reg == `time_base);
assign res_cnt3 = (cnt1_reg == `time_base) & (cnt3_reg == `load_cnt3);
assign cnt3_next = cnt3_reg + 1;
always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1′b0)
cnt3_reg <= 6′d0;
else if(res_cnt3 == 1′b1)
cnt3_reg <= 6′d0;
else if(adv_cnt3 == 1′b1)
cnt3_reg <= cnt3_next;
else
cnt3_reg <= cnt3_reg;
end
/*This is the timer 3 programmed for 25 sec delay. Used for side road traffic*/
assign adv_cnt4 = (start_timer3 == 1′b1) & (cnt1_reg == `time_base);
assign res_cnt4 = (cnt1_reg == `time_base) & (cnt4_reg == `load_cnt4);
assign cnt4_next = cnt4_reg + 1;
always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1′b0)
cnt4_reg <= 8′d0;
else if(res_cnt4 == 1′b1)
cnt4_reg <= 8′d0;
else if(adv_cnt4 == 1′b1)
cnt4_reg <= cnt4_next;
else
cnt4_reg <= cnt4_reg;
end
/*This is the timer 4 programmed for 1 sec delay. Used for blinking of all the yellow lights after the normal traffic hours*/
assign adv_cnt5 = (blink == 1′b1) & (cnt1_reg == `time_base);
assign res_cnt5 = (cnt1_reg == `time_base) & (cnt5_reg == `load_cnt5);
assign cnt5_next = cnt5_reg + 1;
always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1′b0)
cnt5_reg <= 8′d0;
else if(res_cnt5 == 1′b1)
cnt5_reg <= 8′d0;
else if(adv_cnt5 == 1′b1)
cnt5_reg <= cnt5_next;
else
cnt5_reg <= cnt5_reg;
end
/*Traffic light state machine starts here…*/
always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1′b0)
begin
/*Switch of all the lights to start with*/
MG1 <= 1′b0;
MG2 <= 1′b0 ;
SR1 <= 1′b0;
SR2 <= 1′b0;
MY1 <= 1′b0;
MY2 <= 1′b0;
MR1 <= 1′b0;
MR2 <= 1′b0;
SG1 <= 1′b0;
SG2 <= 1′b0;
SY1 <= 1′b0;
SY2 <= 1′b0;
MRT1 <= 1′b0;
MRT2 <= 1′b0;
SRT1 <= 1′b0;
SRT2 <= 1′b0;
/*Also switch off the timers */
start_timer_1 <= 1′b0;
start_timer_2 <= 1′b0;
start_timer_3 <= 1′b0;
state <= `S0;
end
else
case(state)
`S0:
if(blink == 1′b1)
begin
state <= `S8;
end
else
begin
/*Switch ON main green lights and side red lights */
MG1 <= 1′b1;
MG2 <= 1′b1 ;
SR1 <= 1′b1;
SR2 <= 1′b1;
/*Switch of all other lights*/
MY1 <= 1′b0;
MY2 <= 1′b0;
MR1 <= 1′b0;
MR2 <= 1′b0;
SG1 <= 1′b0;
SG2 <= 1′b0;
SY1 <= 1′b0;
SY2 <= 1′b0;
MRT1 <= 1′b0;
MRT2 <= 1′b0;
SRT1 <= 1′b0;
SRT2 <= 1′b0;
if(res_cnt2 == 1′b1)
begin
start_timer1_1 <= 1′b0;
state <= `S1;
end
else
begin
start_timer_1 <= 1′b1;
state <= `S0;
end
end
‘S1:
begin
/*Switch on main yellow lights and side road red lights*/
MY1 <= 1′b1;
MY2 <= 1′b1;
SR1 <= 1′b1;
SR2 <= 1′b1;
/*Switch of all other lights*/
MG1 <= 1′b0;
MG2 <= 1′b0 ;
MR1 <= 1′b0;
MR2 <= 1′b0;
SG1 <= 1′b0;
SG2 <= 1′b0;
SY1 <= 1′b0;
SY2 <= 1′b0;
MRT1 <= 1′b0;
MRT2 <= 1′b0;
SRT1 <= 1′b0;
SRT2 <= 1′b0;
if(res_cnt3 == 1′b1)
begin
start_timer_2 <= 1′b0;
state <= `S2;
end
else
begin
start_timer_2 <= 1′b1;
state <= `S1;
end
end
`S2:
begin
/*Switch ON main red lights, side red lights and main turn lights*/
MRT1 <= 1′b1;
MRT2 <= 1′b1;
SR1 <= 1′b1;
SR2 <= 1′b1;
MR1 <= 1′b1;
MR2 <= 1′b1;
/*Switch of all other lights*/
MG1 <= 1′b0;
MG2 <= 1′b0;
MY1 <= 1′b0;
MY2 <= 1′b0;
SG1 <= 1′b0;
SG2 <= 1′b0;
SY1 <= 1′b0;
SY2 <= 1′b0;
MRT1 <= 1′b0;
MRT2 <= 1′b0;
SRT1 <= 1′b0;
SRT2 <= 1′b0;
if(res_cnt4 == 1′b1)
begin
start_timer_3 <= 1′b0;
state <= `S3;
end
else
begin
start_timer_3 <= 1′b1;
state <= `S2;
end
end
`S3:
begin
/*Switch ON main yellow lights and side red lights*/
MY1 <= 1′b1;
MY2 <= 1′b1;
MR1 <= 1′b1;
MR2 <= 1′b1;
/*Switch of all other lights*/
MG1 <= 1′b0;
MG2 <= 1′b0;
SY1 <= 1′b0;
SY2 <= 1′b0;
MRT1 <= 1′b0;
MRT2 <= 1′b0;
SRT1 <= 1′b0;
SRT2 <= 1′b0;
MRT1 <= 1′b0;
MRT2 <= 1′b0;
SR1 <= 1′b0;
SR2 <= 1′b0;
SG1 <= 1′b0;
SG2 <= 1′b0;
if(res_cnt3 == 1′b1)
begin
start_timer_2 <= 1′b0;
state <= `S4;
end
else
begin
start_timer_3 <= 1′b1;
state <= `S3;
end
end
`S4:
begin
/*Switch ON main red lights and side green lights*/
SG1 <= 1′b1;
SG2 <= 1′b1;
MR1 <= 1′b1;
MR2 <= 1′b1;
/*Switch of all other lights*/
MG1 <= 1′b0;
MG2 <= 1′b0;
MY1 <= 1′b0;
MY2 <= 1′b0;
SY1 <= 1′b0;
SY2 <= 1′b0;
MRT1 <= 1′b0;
MRT2 <= 1′b0;
SRT1 <= 1′b0;
SRT2 <= 1′b0;
MRT1 <= 1′b0;
MRT2 <= 1′b0;
SR1 <= 1′b0;
SR2 <= 1′b0;
if(res_cnt4 == 1′b1)
begin
start_timer_3 <= 1′b0;
state <= `S5;
end
else
begin
start_timer_3 <= 1′b1;
state <= `S4;
end
end
`S5:
begin
/*Switch ON main red lights and side yellow lights*/
SY1 <= 1′b1;
SY2 <= 1′b1;
MR1 <= 1′b1;
MR2 <= 1′b1;
/*Switch of all other lights*/
MG1 <= 1′b0;
MG2 <= 1′b0;
MY1 <= 1′b0;
MY2 <= 1′b0;
SY1 <= 1′b0;
SY2 <= 1′b0;
MRT1 <= 1′b0;
MRT2 <= 1′b0;
SRT1 <= 1′b0;
SRT2 <= 1′b0;
MRT1 <= 1′b0;
MRT2 <= 1′b0;
SR1 <= 1′b0;
SR2 <= 1′b0;
SG1 <= 1′b0;
SG2 <= 1′b0;
if(res_cnt3 == 1′b1)
begin
start_timer_2 <= 1′b0;
state <= `S6;
end
else
begin
start_timer_2 <= 1′b1;
state <= `S5;
end
end
`S5:
begin
/*Switch ON main red lights and side red lights and side turn ights*/
SR1 <= 1′b1;
SR2 <= 1′b1;
MR1 <= 1′b1;
MR2 <= 1′b1;
SRT1 <= 1′b1;
SRT2 <= 1′b1;
/*Switch of all other lights*/
MG1 <= 1′b0;
MG2 <= 1′b0;
MY1 <= 1′b0;
MY2 <= 1′b0;
SY1 <= 1′b0;
SY2 <= 1′b0;
MRT1 <= 1′b0;
MRT2 <= 1′b0;
MRT1 <= 1′b0;
MRT2 <= 1′b0;
SG1 <= 1′b0;
SG2 <= 1′b0;
SY1 <= 1′b0;
SY2 <= 1′b0;
if(res_cnt4 == 1′b1)
begin
start_timer_3 <= 1′b0;
state <= `S7;
end
else
begin
start_timer_3 <= 1′b1;
state <= `S6;
end
end
`S7:
begin
/*Switch ON main red lights and side yellow lights and side red lights*/
SR1 <= 1′b1;
SR2 <= 1′b1;
MR1 <= 1′b1;
MR2 <= 1′b1;
SY1 <= 1′b1;
SY2 <= 1′b1;
/*Switch off all other lights not wanted*/
MG1 <= 1′b0;
MG2 <= 1′b0;
MY1 <= 1′b0;
MY2 <= 1′b0;
MRT1 <= 1′b0;
MRT2 <= 1′b0;
MRT1 <= 1′b0;
MRT2 <= 1′b0;
SG1 <= 1′b0;
SG2 <= 1′b0;
SY1 <= 1′b0;
SY2 <= 1′b0;
SRT1 <= 1′b0;
SRT2 <= 1′b0;
if(res_cnt3 == 1′b1)
begin
start_timer_2 <= 1′b0;
state <= `S0;
end
else
begin
start_timer_3 <= 1′b1;
state <= `S7;
end
end
`S8:
begin
if(blink == 1`b1)
begin
begin
/*Switch OFF all other lights*/
SR1 <= 1′b0;
SR2 <= 1′b0;
MR1 <= 1′b0;
MR2 <= 1′b0;
MG1 <= 1′b0;
MG2 <= 1′b0;
MRT1 <= 1′b0;
MRT2 <= 1′b0;
MRT1 <= 1′b0;
MRT2 <= 1′b0;
SG1 <= 1′b0;
SG2 <= 1′b0;
SY1 <= 1′b0;
SY2 <= 1′b0;
SRT1 <= 1′b0;
SRT2 <= 1′b0;
end
if((cnt_reg == ‘timebase) && (cnt5_reg == load_cnt5))
begin
SY1 <= ~SY1 ;
SY2 <= ~SY2 ;
MY1 <= ~MY1;
MY2 <= ~MY1 ;
end
state <= `S8;
end
else
state <= `S0;
endcase
end
endmodule
end
Test Bench File
/*Test bench for the traffic light controller- traffic_controller_test.v*/
‘define clkperiodby2 10
/*10ns is the half time period freq of operation:50MHz */
`include “traffic_controller.v”
module traffic_controller_test ;
reg clk;
reg reset_n;
reg blink;
traffic_controller tcl(
.clk(clk),
.reset_n(reset_n),
.MG1(MG1),
.MG1(MG2),
.SR1(SR1),
.SR2(SR2),
.MY1(MY1),
.MY2(MY2),
.MR1(MR1),
.MR2(MR2),
.SG1(SG1),
.SG2(SG2),
.SY1(SY1),
.SY2(SY2),
.MRT1(MRT1),
.MRT2(MRT2),
.SRT1(SRT1),
.SRT2(SRT2),
.blink(blink)
);
initial
begin
clk = 1′b0;
reset_n = 1′b0;
blink = 0;
#20 reset_n = 1′b0;
#20 reset_n = 1′b1;
#30000 blink = 1;
#5000 blink = 0;
#400000
$stop
end
always
# `clkperiodby2 clk <= ~clk;
endmodule
Static RAM
Each cell in a static RAM is implemented using a flip flop which is implemented using several MSOFET transistors. External power is required to operate the transistor. As long as, the external power is applied, the static memory cell retains the data. The circuit of a single flip flop based cell which can store a binary 0 and 1 is shown;
Figure: Static cell based on a flip flop
Dynamic RAM
In dynamic RAM, a single memory cell is therefore, implemented using a single transistor and a capacitor which occupy lesser space as compared to six transistor which are used to implement a single static cell. Therefore, the density of capacitor based memory is significantly increased. The capacitor based memory is known as dynamic RAM (DRAM). The circuit diagram of a single DRAM capacitor based memory cell is shown;
Figure: Writing a 1 or 0 into the DRAM cell
Figure: Reading a 1 or 0 from DRAM cell
Figure: Refreshing a DRAM cell
Mask ROM
The storage cell in a mask ROM is implemented using a MOS transistor. The structure of a storage cell in a mask ROM is shown;
Figure: Cell storing a logic 1 or logic 0
Flash Memory
The high density flash memory cell is implemented using a single floating gate MOS transistor.
Figure: Programming with logic 0 and logic 1
Figure: Read operation to read logic 0 and logic 1
Figure: Erase operation of the FLASH memory cell
8 bit Serial In/ Parallel out shift register
An 8 bit serial in / parallel out register based on an identical D type flip flop is shown;
Figure: 8 bit Serial In/ Parallel out shift register
Implementation on PLD
An 8 bit Serial In/ Parallel out register is implemented using the GAL22V10 PLD. The D flip flop implemented in the OLMC is triggered on the positive clock edge. It also has active high asynchronous set and clear inputs.
Module Right_bit_shift_register
Title ‘8-bit shift register in a GAL22V10’
“Device Declaration
Register Device ‘P22V10’
“Pin Declaration
Clock, Clear Pin 1, 2;
Data, Enable Pin 3, 4;
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 Pin 16, 17, 18, 19, 20, 21, 22, 23 ISTYPE ‘reg.buffer’;
Equations
Q0 := Data & Enable;
[Q1, Q2, Q3, Q4, Q5, Q6, Q7] := [Q0, Q1, Q2, Q3, Q4, Q5, Q6];
[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7].CLK = clock;
[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7].AR = !clear;
Test_Vectors
([Clock, Clear, Data, Enable] -> [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7])
[ .x. , 0 , .x. , .x. ] -> [0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 1 , 0 ] -> [0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 0 , 1 ] -> [0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 1 , 1 ] -> [1 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 0 , 1 ] -> [0 , 1 , 0 , 0 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 1 , 1 ] -> [1 , 0 , 1 , 0 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 0 , 1 ] -> [0 , 1 , 0 , 1 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 1 , 1 ] -> [1 , 0 , 1 , 0 , 1 , 0 , 0 , 0 ];
[ .c. , 1 , 0 , 1 ] -> [0 , 1 , 0 , 1 , 0 , 1 , 0 , 0 ];
[ .c. , 1 , 1 , 1 ] -> [1 , 0 , 1 , 0 , 1 , 0 , 1 , 0 ];
[ .c. , 1 , 0 , 1 ] -> [0 , 1 , 0 , 1 , 0 , 1 , 0 , 1 ];
[ .c. , 1 , 1 , 1 ] -> [1 , 0 , 1 , 0 , 1 , 0 , 1 , 0 ];
[ .c. , 0 , 1 , 1 ] -> [0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ];
END
Design of Digital Clock circuit
In digital clock circuit, the 50 Hz, 220 volts ac main sinusoidal signal is shaped into a 50Hz, a 5 volt square wave signal. A divide by 50 counters divides the input 50 Hz signal to a 1 Hz signal. The seconds, divide by 60 counter counts up to 60 seconds (0 to 59). The minutes, divide by 60 counter also counts up to sixty minutes (0 to 59). The hours, decade counter counts from 0 to 9. The flip flop connected to the output of the decade counter is set to 0 or 1 to represent hours from 0 to 9and 10 to 12 respectively.
Figure: Digital clock circuit
Divide by 60 counters
Divide by 60 counters is implemented by cascading two 74HC160A counters. The following diagram shows its implementation.
Figure: Divide by 60 minutes and seconds counter
ALU design with resisters
Microprocessor use multi-bit flip-flops to store information. These multi-bit flip-flops are known as registers. These registers for example, can store data generated at the output of the ALU. The registers can also be used to exchange or copy data. A register is a set of flip-flops connected in parallel to store multi-bit binary information. The clock inputs of all the flip-flops are connected together, to allow simultaneous latching of the multi-bit input data.
Figure: ALU design with registers
Arithmetic and logic unit
Microprocessors have arithmetic and logic units, a combinational circuit that can perform any of the arithmetic operation and logic operations on two input values. The operation to be performed is selected by set of inputs know as function select inputs. The function table of 74XX381 4 bit ALU is shown;
Table: Function select inputs for 74XX381
16 bit atithmetic logic unit
The following shows the 16 bit ALU;
Figure: 16 bit arithmetic and logic unit
An 8 bit Adder/Subtractor Unit
Two 4 bit 74LS283 chips can be cascaded together to form an 8 bit parallel adder unit. Each of the two 74LS283 IC(s) is connected to the 1st complement circuitry that allows either the un-complemented form for subtraction to be applied at the inputs of the two 74LS283 IC(s).
Two set of AND – OR based circuit that allows complemented and non complemented B input to be applied at the B input of the two 4 bit adders. The add/ Subtract function select input are tied together. The carry-In of the 1st 4 bit adder circuit is connected to the add / subtract function select input. The carry-out of the 1st 4 adder circuit is connected to the carry-In of the 2nd 4 bit adder circuit.
Figure: 8 bit Adder/ Subtractor circuit
Consider two numbers A = 103 and B = 67 which are first added and then subtracted using the 8 bit Adder/ Subtractor circuit.
Table: Adding 103 and 67
Table: Subtracting 103 and 67
