ALU design with registers

ALU design with resisters  
Microprocessor use multi-bit flip-flops to store information. These multi-bit flip-flops are known as registers. These registers for example, can store data generated at the output of the ALU. The registers can also be used to exchange or copy data.  A register is a set of flip-flops connected in parallel to store multi-bit binary information. The clock inputs of all the flip-flops are connected together, to allow simultaneous latching of the multi-bit input data.

Figure: ALU design with registers

Arithmetic and logic unit

Arithmetic and logic unit
Microprocessors have arithmetic and logic units, a combinational circuit that can perform any of the arithmetic operation and logic operations on two input values.  The operation to be performed is selected by set of inputs know as function select inputs. The function table of 74XX381 4 bit ALU is shown;

Table: Function select inputs for 74XX381

16 bit atithmetic logic unit

The following shows the 16 bit ALU;

Figure: 16 bit arithmetic and logic unit 

An 8 bit Adder/Subtractor Unit

An 8 bit Adder/Subtractor Unit
Two 4 bit 74LS283 chips can be cascaded together to form an 8 bit parallel adder unit. Each of the two 74LS283 IC(s) is connected to the 1st complement circuitry that allows either the un-complemented form for subtraction to be applied at the inputs of the two 74LS283 IC(s).
Two set of AND – OR based circuit that allows complemented and non complemented B input to be applied at the B input of the two 4 bit adders. The add/ Subtract function select input are tied together. The carry-In of the 1st 4 bit adder circuit is connected to the add / subtract function select input. The carry-out of the 1st 4 adder circuit is connected to the carry-In of the 2nd 4 bit adder circuit.

Figure: 8 bit Adder/ Subtractor circuit

Consider two numbers A = 103 and B = 67 which are first added and then subtracted using the 8 bit Adder/ Subtractor circuit.

Table: Adding 103 and 67

Table: Subtracting 103 and 67

Types of IC Logic gates

Types of IC Logic gates
The most common from of logic gate ICs are listed. To identify and us e the integrated circuits or ICs in implementation logic circuits, some sort of identification code has to be used which is printed on the IC package

Logic gates are identified by the codes. The prefix 74 is used to identify a commercial version of the device from the military version device identified by the prefix 54. Military versions are designed to with stand harsh and severe environment conditions. The XX part of the code identifies the switching speed of the gate.

74XX00: Quad 2 – input NAND gate

74XX02: Quad 2 – input NOR gate

74XX04: Hex Inverter

74XX08: Quad 2 – input AND gate

74XX10: Triple 3 – input AND gate

74XX11: Triple 3 – input AND gate

74XX20: Dual 4 – input NAND gate

74XX21: Dual 2 – input AND gate

74XX27: Triple 3 – input NOR gate

74XX30: Single 8 – input NAND gate

74XX32: Quad 2 – input OR gate

74XX86: Quad 2 – input XOR gate

74XX133: Single 13 – input NAND gate

Caveman number system

Caveman number system
A number system discovered by archaeologists in a prehistoric cave indicates that the caveman used a number system that has 5 distinct shapes ∑, ∆,>, ῼ and ↑. Furthermore; it has been determined that the symbols ∑ to ↑ represents the decimal equivalents 0 to 5 respectively.
Centuries ago a caveman returning after a successful hunting expedition records his successful hunt on the cave wall by carving out the numbers ∆↑ represents decimal number 9.

Table: Decimal equivalent of caveman numbers

The Caveman is using a Base-5 number system. A Base-5 number system has five unique symbols representing numbers 0 t0 4. To represent numbers larger then 4, a combination of 2, 3, 4 or more combinations of caveman numbers are used. Therefore, to represent the decimal 5, a two number combination of Caveman number system is used. The most significant digit is ∆ which is equivalent to decimal 1. The least significant digit is ∑ which is equivalent to decimal 0. The five combinations of Caveman numbers having the most significant digit ∆, represent decimal values 5 to 9 respectively. This is similar to the Decimal Number system, where a 2-digit combination of numbers is used to represent values greater then 9. The most significant digit is set to 1 and the least significant digit varies from 0 to 9 to represent the next 10 values after the largest single decimal number digit 9.

The Caveman number ∆↑ can be written in expression from based on the base value 5 and weights 50, 51, 52 etc.
= ∆ * 51 + ↑ * 50 = ∆ * 5 + ↑ * 1
Replacing the Caveman numbers ∆ and ↑ with equivalent decimal values in the expression yields;
= ∆ * 51 + ↑ * 50 = ∆ * 5 + ↑ * 1 = 9

The number ∆ ῼ↑∑ in decimal is represented in expression from as;
= ∆ * 53 + ῼ * 52 + ↑ * 51 + ∑ * 50 = ∆ * 125 + ῼ * 25 + ↑ * 5 + ∑ * 1
Replacing the Caveman numbers with equivalent decimal values in the expression yields;
= (1) * 125 + (3) * 25 + (4) * 5 + (0) * 1 = 125 + 75 + 20 + 0 = 220

Comparator with hysterics

Comparator with hysterics
If the input to a comparator contain large amount of noise, the output will be erratic when V (in) is near the trip point. One way to reduce the effect of noise is by using a comparator with the positive feedback. The positive feedback produces two separate trip points that prevent a noisy input from producing false transitions.

The standard solution for a noisy input is to use a comparator in which input voltage is applied to the inverting input. Because; the feed back voltage is aiding the input voltage, the feedback is positive. A comparator using positive feed back like this is typically called a Schmitt trigger.
The feedback fraction is;

B = R1 / R1 + R2

 
The input voltage must be increased to slightly more then positive BV (sat) to switch the output voltage from positive to negative.
Once; the output is in the negative state. It will remain there indefinitely until input voltage becomes more negative then negative BV (sat), then the output switches from negative to positive.
The equations for non inverting Schmitt trigger are shown;

UTP = R1 / R2 V (sat)

LTP = – R1/R2 V (sat)

 
The ratio of R1 and R2 determines how much hysterics the Schmitt trigger has. A designer can create enough hysterics to prevent unwanted noise triggers.

Experiment on my experiment table

Figure: Positive feedback Schmitt trigger