Memory cells

Static RAM
Each cell in a static RAM is implemented using a flip flop which is implemented using several MSOFET transistors. External power is required to operate the transistor. As long as, the external power is applied, the static memory cell retains the data. The circuit of a single flip flop based cell which can store a binary 0 and 1 is shown;

Figure: Static cell based on a flip flop

Dynamic RAM
In dynamic RAM, a single memory cell is therefore, implemented using a single transistor and a capacitor which occupy lesser space as compared to six transistor which are used to implement a single static cell. Therefore, the density of capacitor based memory is significantly increased. The capacitor based memory is known as dynamic RAM (DRAM). The circuit diagram of a single DRAM capacitor based memory cell is shown;

Figure: Writing a 1 or 0 into the DRAM cell

Figure: Reading a 1 or 0 from DRAM cell

Figure: Refreshing a DRAM cell

Mask ROM
The storage cell in a mask ROM is implemented using a MOS transistor. The structure of a storage cell in a mask ROM is shown;

Figure: Cell storing a logic 1 or logic 0

Flash Memory
The high density flash memory cell is implemented using a single floating gate MOS transistor.

Figure: Programming with logic 0 and logic 1

Figure: Read operation to read logic 0 and logic 1

 

Figure: Erase operation of the FLASH memory cell

8 bit Serial In/ Parallel out shift register

8 bit Serial In/ Parallel out shift register
An 8 bit serial in / parallel out register based on an identical D type flip flop is shown;

Figure: 8 bit Serial In/ Parallel out shift register

Implementation on PLD
An 8 bit Serial In/ Parallel out register is implemented using the GAL22V10 PLD. The D flip flop implemented in the OLMC is triggered on the positive clock edge. It also has active high asynchronous set and clear inputs.

Module Right_bit_shift_register
Title ‘8-bit shift register in a GAL22V10’

“Device Declaration
Register Device ‘P22V10’

“Pin Declaration
Clock, Clear Pin 1, 2;
Data, Enable Pin 3, 4;
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 Pin 16, 17, 18, 19, 20, 21, 22, 23 ISTYPE ‘reg.buffer’;

Equations
Q0 := Data & Enable;
[Q1, Q2, Q3, Q4, Q5, Q6, Q7] := [Q0, Q1, Q2, Q3, Q4, Q5, Q6];
[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7].CLK = clock;
[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7].AR = !clear;

Test_Vectors
([Clock, Clear, Data, Enable] -> [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7])
[ .x. , 0 , .x. , .x. ] -> [0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 1 , 0 ] -> [0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 0 , 1 ] -> [0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 1 , 1 ] -> [1 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 0 , 1 ] -> [0 , 1 , 0 , 0 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 1 , 1 ] -> [1 , 0 , 1 , 0 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 0 , 1 ] -> [0 , 1 , 0 , 1 , 0 , 0 , 0 , 0 ];
[ .c. , 1 , 1 , 1 ] -> [1 , 0 , 1 , 0 , 1 , 0 , 0 , 0 ];
[ .c. , 1 , 0 , 1 ] -> [0 , 1 , 0 , 1 , 0 , 1 , 0 , 0 ];
[ .c. , 1 , 1 , 1 ] -> [1 , 0 , 1 , 0 , 1 , 0 , 1 , 0 ];
[ .c. , 1 , 0 , 1 ] -> [0 , 1 , 0 , 1 , 0 , 1 , 0 , 1 ];
[ .c. , 1 , 1 , 1 ] -> [1 , 0 , 1 , 0 , 1 , 0 , 1 , 0 ];
[ .c. , 0 , 1 , 1 ] -> [0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ];
END

Digital clock

Design of Digital Clock circuit
In digital clock circuit, the 50 Hz, 220 volts ac main sinusoidal signal is shaped into a 50Hz, a 5 volt square wave signal. A divide by 50 counters divides the input 50 Hz signal to a 1 Hz signal.  The seconds, divide by 60 counter counts up to 60 seconds (0 to 59). The minutes, divide by 60 counter also counts up to sixty minutes (0 to 59). The hours, decade counter counts from 0 to 9. The flip flop connected to the output of the decade counter is set to 0 or 1 to represent hours from 0 to 9and 10 to 12 respectively.


Figure: Digital clock circuit

Divide by 60 counters
Divide by 60 counters is implemented by cascading two 74HC160A counters. The following diagram shows its implementation. 

Figure: Divide by 60 minutes and seconds counter