Traffic Light Controller

Traffic Light Controller
A road intersection is shown on the diagram; on each section of the road
two sensors determine the presence and arrival of vehicles. Sensor 1 is activated if a car is waiting and Sensor 2 is activated when an arriving vehicle passes over the sensor. The sensors installed on the North and South section of the road are connected together and determine the presence of vehicle(s) on the North-South section of the road. The sensors installed on the East and West section of the road are connected together and determine the presence of vehicle(s) on the East-West section of the Road.

Figure: The traffic signals and sensors at traffic intersection.

Verilog code and test bench files
The following is the Verilog design files and test bench for the traffic light controller;
Code is simulated on ModelSim, synplify and XSV FPGA board;
/*traffic_Controller.v*/
`define S0 3’d0
`define S1 3’d1
`define S2 3’d2
`define S3 3’d3
`define S4 3’d4
`define S5 3’d5
`define S6 3’d6
`define S7 3’d7
`define S8 3’d8
‘define time_base 22’d9
/* 22’d9 is used only for simulation purpose- For 40Mhz operation; the time base
is 0.1 sec.
Change 22’d9 to 22d3999999 for 40Mz frequency */
‘define load_cnt2 9’d449
/* This is timer 1 count value in units if 0.1 sec providing 45 sec delay. */
‘define load_cnt3 6’d49
/*This is the time 2 count value in the units of 0.1 sec, providing 5 sec delay.*/
‘define load_cnt4 9’d249
/*This is the timer 3 count value in the units of 0.1 sec providing 1 sec delay*/
module traffic_controller(clk,
reset_n,
MG1,
MG2,
SR1,
SR2,
MY1,
MY2,
MR1,
MR2,
SG1,
SG2,
SY1,
SY2,
MRT1,
MRT2,
SRT1,
SRT2,
blink
);

/*Declear input and outputs */
input clk;
input reset_n;
input blink;
output MG1;
output MG2;
output SR1;
output SR2;
output MY1;
output MY2;
output MR1;
output MR2;
output SG1;
output SG2;
output SY1;
output SY2;
output MRT1;
output MRT2;
output SRT1;
output SRT2;

/*Declear combinational circuits outputs */
wire adv_cnt2;
wire adv_cnt3;
wire adv_cnt4;
wire res_cnt1;
wire res_cnt2;
wire res_cnt3;
wire res_cnt4;
wire [21:0] cnt1_next;
wire [8:0] cnt2_next;
wire [5:0] cnt3_next;
wire [7:0] cnt4_next;
wire [7:0] cnt5_next;

/* Declear register signals */
reg [21:0] cnt1_reg;
reg [8:0] cnt2_reg;
reg [5:0] cnt3_reg;
reg [7:0] cnt4_reg;
reg [7:0] cnt5_reg;
reg start_timer_1;
reg start_timer_2;
reg start_timer_3;
reg [2:0] state;
reg MG1;
reg MG2;
reg SR1;
reg SR2;
reg MY1;
reg MY2;
reg MR1;
reg MR2;
reg SG1;
reg SG2;
reg SY1;
reg SY2;
reg MRT1;
reg MRT2;
reg SRT1;
reg SRT2;

/*Timer implementation starts here */
assign cnt1_next = cnt1_reg + 1;
always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1’b0)
cnt1_reg <= 22’d0;
else if(cnt_reg == `time_base)
cnt1_reg <= 22’d0;
else
cnt1_reg <= cnt1_next;
end
/* This is a timer 1 programmed for 45 sec in order to facilitate the smooth run of the
main road traffic */
assign adv_cnt2 = (start_timer_1 == 1’b1) & (cnt1_reg == `time_base);
assign res_cnt2 = (cnt1_reg == `time_base) & (count2_reg == `load_cnt2)
assign cnt2_next = cnt2_reg + 1;
always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1’b0)
cnt2_reg <= 9’d0;
else if(res_cnt2 == 1’b1)
cnt2_reg <= 9’d0;
else if(adv_cnt2 == 1’b1)
cnt3_reg <= cnt3_next;
else
cnt2_reg <= cnt2_reg;
end

/*This is the timer 2 programmed for 5 sec. Activating yellow lights for the smoth transitaion while switching from one traffic to another */
assign adv_cnt3 = (start_timer2 == 1’b1) & (cnt1_reg == `time_base);
assign res_cnt3 = (cnt1_reg == `time_base) & (cnt3_reg == `load_cnt3);
assign cnt3_next = cnt3_reg + 1;
always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1’b0)
cnt3_reg <= 6’d0;
else if(res_cnt3 == 1’b1)
cnt3_reg <= 6’d0;
else if(adv_cnt3 == 1’b1)
cnt3_reg <= cnt3_next;
else
cnt3_reg <= cnt3_reg;
end
/*This is the timer 3 programmed for 25 sec delay. Used for side road traffic*/
assign adv_cnt4 = (start_timer3 == 1’b1) & (cnt1_reg == `time_base);
assign res_cnt4 = (cnt1_reg == `time_base) & (cnt4_reg == `load_cnt4);
assign cnt4_next = cnt4_reg + 1;
always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1’b0)
cnt4_reg <= 8’d0;
else if(res_cnt4 == 1’b1)
cnt4_reg <= 8’d0;
else if(adv_cnt4 == 1’b1)
cnt4_reg <= cnt4_next;
else
cnt4_reg <= cnt4_reg;
end

/*This is the timer 4 programmed for 1 sec delay. Used for blinking of all the yellow lights after the normal traffic hours*/
assign adv_cnt5 = (blink == 1’b1) & (cnt1_reg == `time_base);
assign res_cnt5 = (cnt1_reg == `time_base) & (cnt5_reg == `load_cnt5);
assign cnt5_next = cnt5_reg + 1;

always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1’b0)
cnt5_reg <= 8’d0;
else if(res_cnt5 == 1’b1)
cnt5_reg <= 8’d0;
else if(adv_cnt5 == 1’b1)
cnt5_reg <= cnt5_next;
else
cnt5_reg <= cnt5_reg;
end

/*Traffic light state machine starts here…*/
always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1’b0)
begin
/*Switch of all the lights to start with*/
MG1 <= 1’b0;
MG2 <= 1’b0 ;
SR1 <= 1’b0;
SR2 <= 1’b0;
MY1 <= 1’b0;
MY2 <= 1’b0;
MR1 <= 1’b0;
MR2 <= 1’b0;
SG1 <= 1’b0;
SG2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SRT1 <= 1’b0;
SRT2 <= 1’b0;
/*Also switch off the timers */
start_timer_1 <= 1’b0;
start_timer_2 <= 1’b0;
start_timer_3 <= 1’b0;
state <= `S0;
end
else
case(state)
`S0:
if(blink == 1’b1)
begin
state <= `S8;
end
else
begin
/*Switch ON main green lights and side red lights */
MG1 <= 1’b1;
MG2 <= 1’b1 ;
SR1 <= 1’b1;
SR2 <= 1’b1;
/*Switch of all other lights*/
MY1 <= 1’b0;
MY2 <= 1’b0;
MR1 <= 1’b0;
MR2 <= 1’b0;
SG1 <= 1’b0;
SG2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SRT1 <= 1’b0;
SRT2 <= 1’b0;
if(res_cnt2 == 1’b1)
begin
start_timer1_1 <= 1’b0;
state <= `S1;
end
else
begin
start_timer_1 <= 1’b1;
state <= `S0;
end
end
‘S1:
begin
/*Switch on main yellow lights and side road red lights*/
MY1 <= 1’b1;
MY2 <= 1’b1;
SR1 <= 1’b1;
SR2 <= 1’b1;
/*Switch of all other lights*/
MG1 <= 1’b0;
MG2 <= 1’b0 ;
MR1 <= 1’b0;
MR2 <= 1’b0;
SG1 <= 1’b0;
SG2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SRT1 <= 1’b0;
SRT2 <= 1’b0;
if(res_cnt3 == 1’b1)
begin
start_timer_2 <= 1’b0;
state <= `S2;
end
else
begin
start_timer_2 <= 1’b1;
state <= `S1;
end
end
`S2:
begin
/*Switch ON main red lights, side red lights and main turn lights*/
MRT1 <= 1’b1;
MRT2 <= 1’b1;
SR1 <= 1’b1;
SR2 <= 1’b1;
MR1 <= 1’b1;
MR2 <= 1’b1;
/*Switch of all other lights*/
MG1 <= 1’b0;
MG2 <= 1’b0;
MY1 <= 1’b0;
MY2 <= 1’b0;
SG1 <= 1’b0;
SG2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SRT1 <= 1’b0;
SRT2 <= 1’b0;
if(res_cnt4 == 1’b1)
begin
start_timer_3 <= 1’b0;
state <= `S3;
end
else
begin
start_timer_3 <= 1’b1;
state <= `S2;
end
end
`S3:
begin
/*Switch ON main yellow lights and side red lights*/
MY1 <= 1’b1;
MY2 <= 1’b1;
MR1 <= 1’b1;
MR2 <= 1’b1;
/*Switch of all other lights*/
MG1 <= 1’b0;
MG2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SRT1 <= 1’b0;
SRT2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SR1 <= 1’b0;
SR2 <= 1’b0;
SG1 <= 1’b0;
SG2 <= 1’b0;
if(res_cnt3 == 1’b1)
begin
start_timer_2 <= 1’b0;
state <= `S4;
end
else
begin
start_timer_3 <= 1’b1;
state <= `S3;
end
end
`S4:
begin
/*Switch ON main red lights and side green lights*/
SG1 <= 1’b1;
SG2 <= 1’b1;
MR1 <= 1’b1;
MR2 <= 1’b1;
/*Switch of all other lights*/
MG1 <= 1’b0;
MG2 <= 1’b0;
MY1 <= 1’b0;
MY2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SRT1 <= 1’b0;
SRT2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SR1 <= 1’b0;
SR2 <= 1’b0;
if(res_cnt4 == 1’b1)
begin
start_timer_3 <= 1’b0;
state <= `S5;
end
else
begin
start_timer_3 <= 1’b1;
state <= `S4;
end
end
`S5:
begin
/*Switch ON main red lights and side yellow lights*/
SY1 <= 1’b1;
SY2 <= 1’b1;
MR1 <= 1’b1;
MR2 <= 1’b1;
/*Switch of all other lights*/
MG1 <= 1’b0;
MG2 <= 1’b0;
MY1 <= 1’b0;
MY2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SRT1 <= 1’b0;
SRT2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SR1 <= 1’b0;
SR2 <= 1’b0;
SG1 <= 1’b0;
SG2 <= 1’b0;
if(res_cnt3 == 1’b1)
begin
start_timer_2 <= 1’b0;
state <= `S6;
end
else
begin
start_timer_2 <= 1’b1;
state <= `S5;
end
end
`S5:
begin
/*Switch ON main red lights and side red lights and side turn ights*/
SR1 <= 1’b1;
SR2 <= 1’b1;
MR1 <= 1’b1;
MR2 <= 1’b1;
SRT1 <= 1’b1;
SRT2 <= 1’b1;
/*Switch of all other lights*/
MG1 <= 1’b0;
MG2 <= 1’b0;
MY1 <= 1’b0;
MY2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SG1 <= 1’b0;
SG2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
if(res_cnt4 == 1’b1)
begin
start_timer_3 <= 1’b0;
state <= `S7;
end
else
begin
start_timer_3 <= 1’b1;
state <= `S6;
end
end
`S7:
begin
/*Switch ON main red lights and side yellow lights and side red lights*/
SR1 <= 1’b1;
SR2 <= 1’b1;
MR1 <= 1’b1;
MR2 <= 1’b1;
SY1 <= 1’b1;
SY2 <= 1’b1;
/*Switch off all other lights not wanted*/
MG1 <= 1’b0;
MG2 <= 1’b0;
MY1 <= 1’b0;
MY2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SG1 <= 1’b0;
SG2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
SRT1 <= 1’b0;
SRT2 <= 1’b0;
if(res_cnt3 == 1’b1)
begin
start_timer_2 <= 1’b0;
state <= `S0;
end
else
begin
start_timer_3 <= 1’b1;
state <= `S7;
end
end
`S8:
begin
if(blink == 1`b1)
begin
begin
/*Switch OFF all other lights*/
SR1 <= 1’b0;
SR2 <= 1’b0;
MR1 <= 1’b0;
MR2 <= 1’b0;
MG1 <= 1’b0;
MG2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SG1 <= 1’b0;
SG2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
SRT1 <= 1’b0;
SRT2 <= 1’b0;
end
if((cnt_reg == ‘timebase) && (cnt5_reg == load_cnt5))
begin
SY1 <= ~SY1 ;
SY2 <= ~SY2 ;
MY1 <= ~MY1;
MY2 <= ~MY1 ;
end
state <= `S8;
end
else
state <= `S0;
endcase
end
endmodule
end

Test Bench File
/*Test bench for the traffic light controller- traffic_controller_test.v*/
‘define clkperiodby2 10
/*10ns is the half time period freq of operation:50MHz */
`include “traffic_controller.v”

module traffic_controller_test ;
reg clk;
reg reset_n;
reg blink;

traffic_controller tcl(
.clk(clk),
.reset_n(reset_n),
.MG1(MG1),
.MG1(MG2),
.SR1(SR1),
.SR2(SR2),
.MY1(MY1),
.MY2(MY2),
.MR1(MR1),
.MR2(MR2),
.SG1(SG1),
.SG2(SG2),
.SY1(SY1),
.SY2(SY2),
.MRT1(MRT1),
.MRT2(MRT2),
.SRT1(SRT1),
.SRT2(SRT2),
.blink(blink)
);

initial
begin
clk = 1’b0;
reset_n = 1’b0;
blink = 0;
#20 reset_n = 1’b0;
#20 reset_n = 1’b1;

#30000 blink = 1;
#5000 blink = 0;

#400000
$stop
end
always
# `clkperiodby2 clk <= ~clk;
endmodule

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