Category Archives: Electronics and Communication

This contains topics related to analog,digital electronics and wireless communication and protocols.

Smart Antenna?

Smart Antenna?
Smart Antenna is an antenna array aided by some “smart” algorithm to combine the signals, designed to adapt to different signal environments. The antenna can automatically adjust to a dynamic signal Environment. The gain of the antenna for a given direction of arrival is adjustable. In truth, antennas are not smart, antenna systems are smart. Generally collocated with a base station, a smart antenna system combines an antenna array with a digital signal-processing capability to transmit and receive in an adaptive, spatially sensitive manner. In other words, such a system can automatically change the directionality of its radiation patterns in response to its signal environment. This can dramatically increase the performance characteristics (such as capacity) of a wireless system.

Types of Smart Antenna Systems

The following are distinctions between the two major categories of smart antennas regarding the choices in transmit strategy:

Switched Beam Antennas
In Switched Beam Smart antenna, there are a finite number of fixed, predefined patterns or combining strategies (sectors).
Switched beam antenna systems form multiple fixed beams with heightened sensitivity in particular directions. These antenna systems detect signal strength, choose from one of several predetermined, fixed beams, and switch from one beam to another as the mobile moves throughout the sector.  Instead of shaping the directional antenna pattern with the metallic properties and physical design of a single element (like a sectorized antenna), switched beam systems combine the outputs of multiple antennas in such a way as to form finely sectorized (directional) beams with more spatial selectivity than can be achieved with conventional, single-element approaches.
In the Switched Beam scheme, beams are created by choosing a particular set of antenna weights from a fixed “library” of beam weight vectors. The weight vector associated with maximum SNIR is chosen as the current weight vector. It follows that in order to continuously maintain maximum SNIR, the choice of weight vector must be continuously updated via ongoing SNIR measurements.Switched beam systems are simpler and less computationally intensive.

Figure: Switched Beam System Coverage Patterns (Sectors)

Adaptive Array Antennas
In Adaptive Array antenna there are an infinite number of patterns (scenario-based) that are adjusted in real time.
Adaptive antenna technology represents the most advanced smart antenna approach to date. Using a variety of new signal-processing algorithms, the adaptive system takes advantage of its ability to effectively locate and track various types of signals to dynamically minimize interference and maximize intended signal reception. Both systems attempt to increase gain according to the location of the user; however, only the adaptive system provides optimal gain while simultaneously identifying, tracking, and minimizing interfering signals.

Figure: Adaptive Array Coverage, A representative depiction of a Main Lobe extending toward a User with a Null directed toward a Co channel Interferer.

Beamforming Algorithms
In beamforming, both the amplitude and phase of each antenna element are controlled. Combined amplitude and phase control can be used to adjust side lobe levels and steer nulls better than can be achieved by phase control alone. The combined relative amplitude ak and phase shift qk for each antenna is called a “complex weight” and is represented by a complex constant wk (for the kth antenna). These weights are calculated using different algorithms.
Beamforming is the term used to describe the application of weights to the inputs of an array of antennas to focus the reception of the antenna array in a certain direction, called the look direction or the main lobe. More importantly, other signals of the same carrier frequency from other directions can be rejected. These effects are all achieved electronically and no physical movement of the receiving antennas is necessary. In addition, multiple beamformers focused in different directions can share a single antenna array; one set of antennas can service multiple calls of the same carrier.
In Beamforming, we discriminate between signals according to their angles of arrival (AOA). Beam pattern is controlled by the complex weights.

Least-Mean-Squares Algorithm
The LMS algorithm can be considered to be the most common adaptive algorithm for continues adaptation. It uses the steepest-descent method and recursively computes and updates the weight vector.

Figure: LMS Algorithm

Due to the steepest-descend the updated vector will propagate to the vector which causes the least mean square error (MSE) between the beamformer output and the reference signal. The following derivation for the LMS algorithm is found in . The MSE is defined by:

is the complex conjugate of the desired signal. The signal is the received signal from the antenna elements, and is the output of the beamform antenna and is the Hermetian operator. The expected value of both sides leads to:

In this relation the r and R are defined by:

R is referred to as the covariance matrix. If the gradient of the weight vector w is zero, the MSE is at its

minimum. This leads to:

This solution is called the Wiener-Hopf equation for the optimum Wiener solution:

The LMS algorithm converges to this optimum Wiener solution. The basic iteration is based on the

following simple recursive relation:

And combining above two equations, gives:

The measurement of the gradient vector is not possible, and therefore the instantaneous estimate is used.

The LMS algorithm can be written in its final form.

One of the issues on the use of the instantaneous error is concerned with the gradient vector, which is not the true error gradient. The gradient is stochastic and therefore the estimated vector will never be the optimum solution. The steady state solution is noisy; it will fluctuate around the optimum solution. By decreasing µ the precision will improve but it will decrease the adaptation rate. An adaptive µ could solve this issue by starting with a large µ and decrease the factor when the vector converges. When an array of 4 antennas is used, there is a maximum of 3 nulls that can eliminate the interferer. Figure 7 shows the convergence of the array for 2 interferers. The minimum error is a result of the extra ‘system’ noise that is added to all antennas. The interference signals are Gaussian white noise, zero mean with a sigma of 1. The extra system noise to all antennas is white noise with zero mean and a sigma of 0.1. The received signals are MSK signals with an oversampling of 4 and have an amplitude of 1 in the simulations. The true array output y(t) is converging to the desired signal d(t). After 40 samples the signal is at its minimum due to the system noise. The LMS cannot filter the system noise, as it is not correlated for all four antennas. The interferers are cancelled by placing nulls in the direction of the interferers. The received signal arrives at an angle of 25 degrees and the array response is 0 dB. The LMS algorithm clearly works sufficient as the strong interferers are reduced.

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Digital Clock Simulation

Digital Clock
In digital clock circuit, the 50 Hz, 220 volts ac main sinusoidal signal is shaped into a 50Hz, a 5 volt square wave signal. A divide by 50 counters divides the input 50 Hz signal to a 1 Hz signal. The seconds, divide by 60 counter counts up to 60 seconds (0 to 59). The minutes, divide by 60 counter also counts up to sixty minutes (0 to 59). The hours, decade counter counts from 0 to 9. The flip flop connected to the output of the decade counter is set to 0 or 1 to represent hours from 0 to 9and 10 to 12 respectively.

Simulation of Digital Clock
The following figure shows the simulation of the digital clock;

Figure: Digital Clock Simulation

 

Bridge Rectifier Simulation

Full Wave Bridge Rectifier
The bridge rectifier is the most commonly used full wave rectifier circuit for several reasons
(1) It does not require the use of center-tapped transformer, and therefore can be coupled directly to the ac power line, if desired.
(2)Using a transformer with the same secondary voltage produces a peak output voltage that is nearly double the voltage of the full wave center-tapped rectifier. This results in the higher dc voltage from the supply.

Figure: Bridge full wave rectifier

When D1 and D3 are on, D2 and D4 are off and vive versa. This circuit operation is illustrated in the fig.
The current direction will not change in the either condition.

Simulation

The follwing figure shows the simulation of full wave bridge rectifier;

Figure: Simulation of Full Wave Bridge Rectifier

Inverting operation amplifier

Inverting Operation Amplifier
In an inverting amplifier; the output of the voltage changes in opposite direction as that of input voltage. The following figure shows the configuration of Inverting amplifier;

Figure: Inverting operation amplifier

Simulation
The following figure shows the simulation of 741 operation amplifier;

Figure: Simulation of inverting operation amplifier

Serial Communication based Calculator

Serial Communication Based Calculator
Implemented a serial communication based calculator using Proteus. The PIC18F871 PIC was used; it was connected with 20 x 2 alphanumeric LCD. The LCD was used to display the numbers input by the user from a PC connected via serial port with the microcontroller. The below the schematic of the project;

Schematic Design
The below is the schematic design of the project;

Figure: Schematic of Serial communication based calculator

PCB Design
The following shows the PCB design of the project;

Figure: PCB design of serial communication based calculator

Human Speech Processing!

Sound Effects:

We have created some sound effects listed below:
1: Echo
2: Delay
3: Multiple delays
4: Multiple echoes
5: Fade in
6: Fade out

1:ECHO:
The Phenomenon produced when a sound reflects from any obstacle delayed by 100 ms.Or in other words, repetition of a sound by reflection of sound waves from a surface.  Echo rises in Communication systems, when signals encounter a mismatch in impedance.

Figure:Echo Sound Effect

 

ALGORITHM:
We are reading a sound clip from a file into a vector, then we produced the delayed version of the sound (delaying it by 100 ms),then we add the two vectors obtaining the resultant echoed sound clip.

Figure: Graphical View of Echo Sound Effect.

2: MULTIPLE DELAYS:
When we add up a sound clip with itself each delayed by different factor,the resultant is multiple delayed sound effect.

Figure: Multiple Echo Sound Effects.

ALGORITHM:
A) Read a sound clip from a file
B) take input from user number of walls , Nwalls.
C) Input distance of each wall into  Distance vector
D) Calculate delay of each reflected signal into delays vector.
E) Produce the delayed version of original sound by delaying it by delays[i]
F) Sum up the all delayed vectors. The resultant is multiple delayed signal.

Traffic Light Controller

Traffic Light Controller
A road intersection is shown on the diagram; on each section of the road
two sensors determine the presence and arrival of vehicles. Sensor 1 is activated if a car is waiting and Sensor 2 is activated when an arriving vehicle passes over the sensor. The sensors installed on the North and South section of the road are connected together and determine the presence of vehicle(s) on the North-South section of the road. The sensors installed on the East and West section of the road are connected together and determine the presence of vehicle(s) on the East-West section of the Road.

Figure: The traffic signals and sensors at traffic intersection.

Verilog code and test bench files
The following is the Verilog design files and test bench for the traffic light controller;
Code is simulated on ModelSim, synplify and XSV FPGA board;
/*traffic_Controller.v*/
`define S0 3’d0
`define S1 3’d1
`define S2 3’d2
`define S3 3’d3
`define S4 3’d4
`define S5 3’d5
`define S6 3’d6
`define S7 3’d7
`define S8 3’d8
‘define time_base 22’d9
/* 22’d9 is used only for simulation purpose- For 40Mhz operation; the time base
is 0.1 sec.
Change 22’d9 to 22d3999999 for 40Mz frequency */
‘define load_cnt2 9’d449
/* This is timer 1 count value in units if 0.1 sec providing 45 sec delay. */
‘define load_cnt3 6’d49
/*This is the time 2 count value in the units of 0.1 sec, providing 5 sec delay.*/
‘define load_cnt4 9’d249
/*This is the timer 3 count value in the units of 0.1 sec providing 1 sec delay*/
module traffic_controller(clk,
reset_n,
MG1,
MG2,
SR1,
SR2,
MY1,
MY2,
MR1,
MR2,
SG1,
SG2,
SY1,
SY2,
MRT1,
MRT2,
SRT1,
SRT2,
blink
);

/*Declear input and outputs */
input clk;
input reset_n;
input blink;
output MG1;
output MG2;
output SR1;
output SR2;
output MY1;
output MY2;
output MR1;
output MR2;
output SG1;
output SG2;
output SY1;
output SY2;
output MRT1;
output MRT2;
output SRT1;
output SRT2;

/*Declear combinational circuits outputs */
wire adv_cnt2;
wire adv_cnt3;
wire adv_cnt4;
wire res_cnt1;
wire res_cnt2;
wire res_cnt3;
wire res_cnt4;
wire [21:0] cnt1_next;
wire [8:0] cnt2_next;
wire [5:0] cnt3_next;
wire [7:0] cnt4_next;
wire [7:0] cnt5_next;

/* Declear register signals */
reg [21:0] cnt1_reg;
reg [8:0] cnt2_reg;
reg [5:0] cnt3_reg;
reg [7:0] cnt4_reg;
reg [7:0] cnt5_reg;
reg start_timer_1;
reg start_timer_2;
reg start_timer_3;
reg [2:0] state;
reg MG1;
reg MG2;
reg SR1;
reg SR2;
reg MY1;
reg MY2;
reg MR1;
reg MR2;
reg SG1;
reg SG2;
reg SY1;
reg SY2;
reg MRT1;
reg MRT2;
reg SRT1;
reg SRT2;

/*Timer implementation starts here */
assign cnt1_next = cnt1_reg + 1;
always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1’b0)
cnt1_reg <= 22’d0;
else if(cnt_reg == `time_base)
cnt1_reg <= 22’d0;
else
cnt1_reg <= cnt1_next;
end
/* This is a timer 1 programmed for 45 sec in order to facilitate the smooth run of the
main road traffic */
assign adv_cnt2 = (start_timer_1 == 1’b1) & (cnt1_reg == `time_base);
assign res_cnt2 = (cnt1_reg == `time_base) & (count2_reg == `load_cnt2)
assign cnt2_next = cnt2_reg + 1;
always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1’b0)
cnt2_reg <= 9’d0;
else if(res_cnt2 == 1’b1)
cnt2_reg <= 9’d0;
else if(adv_cnt2 == 1’b1)
cnt3_reg <= cnt3_next;
else
cnt2_reg <= cnt2_reg;
end

/*This is the timer 2 programmed for 5 sec. Activating yellow lights for the smoth transitaion while switching from one traffic to another */
assign adv_cnt3 = (start_timer2 == 1’b1) & (cnt1_reg == `time_base);
assign res_cnt3 = (cnt1_reg == `time_base) & (cnt3_reg == `load_cnt3);
assign cnt3_next = cnt3_reg + 1;
always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1’b0)
cnt3_reg <= 6’d0;
else if(res_cnt3 == 1’b1)
cnt3_reg <= 6’d0;
else if(adv_cnt3 == 1’b1)
cnt3_reg <= cnt3_next;
else
cnt3_reg <= cnt3_reg;
end
/*This is the timer 3 programmed for 25 sec delay. Used for side road traffic*/
assign adv_cnt4 = (start_timer3 == 1’b1) & (cnt1_reg == `time_base);
assign res_cnt4 = (cnt1_reg == `time_base) & (cnt4_reg == `load_cnt4);
assign cnt4_next = cnt4_reg + 1;
always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1’b0)
cnt4_reg <= 8’d0;
else if(res_cnt4 == 1’b1)
cnt4_reg <= 8’d0;
else if(adv_cnt4 == 1’b1)
cnt4_reg <= cnt4_next;
else
cnt4_reg <= cnt4_reg;
end

/*This is the timer 4 programmed for 1 sec delay. Used for blinking of all the yellow lights after the normal traffic hours*/
assign adv_cnt5 = (blink == 1’b1) & (cnt1_reg == `time_base);
assign res_cnt5 = (cnt1_reg == `time_base) & (cnt5_reg == `load_cnt5);
assign cnt5_next = cnt5_reg + 1;

always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1’b0)
cnt5_reg <= 8’d0;
else if(res_cnt5 == 1’b1)
cnt5_reg <= 8’d0;
else if(adv_cnt5 == 1’b1)
cnt5_reg <= cnt5_next;
else
cnt5_reg <= cnt5_reg;
end

/*Traffic light state machine starts here…*/
always @(posedge clk or negedge reset_n)
begin
if(reset_n == 1’b0)
begin
/*Switch of all the lights to start with*/
MG1 <= 1’b0;
MG2 <= 1’b0 ;
SR1 <= 1’b0;
SR2 <= 1’b0;
MY1 <= 1’b0;
MY2 <= 1’b0;
MR1 <= 1’b0;
MR2 <= 1’b0;
SG1 <= 1’b0;
SG2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SRT1 <= 1’b0;
SRT2 <= 1’b0;
/*Also switch off the timers */
start_timer_1 <= 1’b0;
start_timer_2 <= 1’b0;
start_timer_3 <= 1’b0;
state <= `S0;
end
else
case(state)
`S0:
if(blink == 1’b1)
begin
state <= `S8;
end
else
begin
/*Switch ON main green lights and side red lights */
MG1 <= 1’b1;
MG2 <= 1’b1 ;
SR1 <= 1’b1;
SR2 <= 1’b1;
/*Switch of all other lights*/
MY1 <= 1’b0;
MY2 <= 1’b0;
MR1 <= 1’b0;
MR2 <= 1’b0;
SG1 <= 1’b0;
SG2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SRT1 <= 1’b0;
SRT2 <= 1’b0;
if(res_cnt2 == 1’b1)
begin
start_timer1_1 <= 1’b0;
state <= `S1;
end
else
begin
start_timer_1 <= 1’b1;
state <= `S0;
end
end
‘S1:
begin
/*Switch on main yellow lights and side road red lights*/
MY1 <= 1’b1;
MY2 <= 1’b1;
SR1 <= 1’b1;
SR2 <= 1’b1;
/*Switch of all other lights*/
MG1 <= 1’b0;
MG2 <= 1’b0 ;
MR1 <= 1’b0;
MR2 <= 1’b0;
SG1 <= 1’b0;
SG2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SRT1 <= 1’b0;
SRT2 <= 1’b0;
if(res_cnt3 == 1’b1)
begin
start_timer_2 <= 1’b0;
state <= `S2;
end
else
begin
start_timer_2 <= 1’b1;
state <= `S1;
end
end
`S2:
begin
/*Switch ON main red lights, side red lights and main turn lights*/
MRT1 <= 1’b1;
MRT2 <= 1’b1;
SR1 <= 1’b1;
SR2 <= 1’b1;
MR1 <= 1’b1;
MR2 <= 1’b1;
/*Switch of all other lights*/
MG1 <= 1’b0;
MG2 <= 1’b0;
MY1 <= 1’b0;
MY2 <= 1’b0;
SG1 <= 1’b0;
SG2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SRT1 <= 1’b0;
SRT2 <= 1’b0;
if(res_cnt4 == 1’b1)
begin
start_timer_3 <= 1’b0;
state <= `S3;
end
else
begin
start_timer_3 <= 1’b1;
state <= `S2;
end
end
`S3:
begin
/*Switch ON main yellow lights and side red lights*/
MY1 <= 1’b1;
MY2 <= 1’b1;
MR1 <= 1’b1;
MR2 <= 1’b1;
/*Switch of all other lights*/
MG1 <= 1’b0;
MG2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SRT1 <= 1’b0;
SRT2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SR1 <= 1’b0;
SR2 <= 1’b0;
SG1 <= 1’b0;
SG2 <= 1’b0;
if(res_cnt3 == 1’b1)
begin
start_timer_2 <= 1’b0;
state <= `S4;
end
else
begin
start_timer_3 <= 1’b1;
state <= `S3;
end
end
`S4:
begin
/*Switch ON main red lights and side green lights*/
SG1 <= 1’b1;
SG2 <= 1’b1;
MR1 <= 1’b1;
MR2 <= 1’b1;
/*Switch of all other lights*/
MG1 <= 1’b0;
MG2 <= 1’b0;
MY1 <= 1’b0;
MY2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SRT1 <= 1’b0;
SRT2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SR1 <= 1’b0;
SR2 <= 1’b0;
if(res_cnt4 == 1’b1)
begin
start_timer_3 <= 1’b0;
state <= `S5;
end
else
begin
start_timer_3 <= 1’b1;
state <= `S4;
end
end
`S5:
begin
/*Switch ON main red lights and side yellow lights*/
SY1 <= 1’b1;
SY2 <= 1’b1;
MR1 <= 1’b1;
MR2 <= 1’b1;
/*Switch of all other lights*/
MG1 <= 1’b0;
MG2 <= 1’b0;
MY1 <= 1’b0;
MY2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SRT1 <= 1’b0;
SRT2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SR1 <= 1’b0;
SR2 <= 1’b0;
SG1 <= 1’b0;
SG2 <= 1’b0;
if(res_cnt3 == 1’b1)
begin
start_timer_2 <= 1’b0;
state <= `S6;
end
else
begin
start_timer_2 <= 1’b1;
state <= `S5;
end
end
`S5:
begin
/*Switch ON main red lights and side red lights and side turn ights*/
SR1 <= 1’b1;
SR2 <= 1’b1;
MR1 <= 1’b1;
MR2 <= 1’b1;
SRT1 <= 1’b1;
SRT2 <= 1’b1;
/*Switch of all other lights*/
MG1 <= 1’b0;
MG2 <= 1’b0;
MY1 <= 1’b0;
MY2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SG1 <= 1’b0;
SG2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
if(res_cnt4 == 1’b1)
begin
start_timer_3 <= 1’b0;
state <= `S7;
end
else
begin
start_timer_3 <= 1’b1;
state <= `S6;
end
end
`S7:
begin
/*Switch ON main red lights and side yellow lights and side red lights*/
SR1 <= 1’b1;
SR2 <= 1’b1;
MR1 <= 1’b1;
MR2 <= 1’b1;
SY1 <= 1’b1;
SY2 <= 1’b1;
/*Switch off all other lights not wanted*/
MG1 <= 1’b0;
MG2 <= 1’b0;
MY1 <= 1’b0;
MY2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SG1 <= 1’b0;
SG2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
SRT1 <= 1’b0;
SRT2 <= 1’b0;
if(res_cnt3 == 1’b1)
begin
start_timer_2 <= 1’b0;
state <= `S0;
end
else
begin
start_timer_3 <= 1’b1;
state <= `S7;
end
end
`S8:
begin
if(blink == 1`b1)
begin
begin
/*Switch OFF all other lights*/
SR1 <= 1’b0;
SR2 <= 1’b0;
MR1 <= 1’b0;
MR2 <= 1’b0;
MG1 <= 1’b0;
MG2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
MRT1 <= 1’b0;
MRT2 <= 1’b0;
SG1 <= 1’b0;
SG2 <= 1’b0;
SY1 <= 1’b0;
SY2 <= 1’b0;
SRT1 <= 1’b0;
SRT2 <= 1’b0;
end
if((cnt_reg == ‘timebase) && (cnt5_reg == load_cnt5))
begin
SY1 <= ~SY1 ;
SY2 <= ~SY2 ;
MY1 <= ~MY1;
MY2 <= ~MY1 ;
end
state <= `S8;
end
else
state <= `S0;
endcase
end
endmodule
end

Test Bench File
/*Test bench for the traffic light controller- traffic_controller_test.v*/
‘define clkperiodby2 10
/*10ns is the half time period freq of operation:50MHz */
`include “traffic_controller.v”

module traffic_controller_test ;
reg clk;
reg reset_n;
reg blink;

traffic_controller tcl(
.clk(clk),
.reset_n(reset_n),
.MG1(MG1),
.MG1(MG2),
.SR1(SR1),
.SR2(SR2),
.MY1(MY1),
.MY2(MY2),
.MR1(MR1),
.MR2(MR2),
.SG1(SG1),
.SG2(SG2),
.SY1(SY1),
.SY2(SY2),
.MRT1(MRT1),
.MRT2(MRT2),
.SRT1(SRT1),
.SRT2(SRT2),
.blink(blink)
);

initial
begin
clk = 1’b0;
reset_n = 1’b0;
blink = 0;
#20 reset_n = 1’b0;
#20 reset_n = 1’b1;

#30000 blink = 1;
#5000 blink = 0;

#400000
$stop
end
always
# `clkperiodby2 clk <= ~clk;
endmodule